Image
|
Figure Caption
Fig. 10 Pictorial representation of INHIBIT logic gate of S3 (a) and its corresponding truth table (b), and schematic illustration of the reversible logic-operation for the memory element featuring ‘write-read-erase-read’ ̀ processes utilizing Zn2+ cations and EDTA.
Acknowledgments
This image is the copyrighted work of the attributed author or publisher, and
ZFIN has permission only to display this image to its users.
Additional permissions should be obtained from the applicable author or publisher of the image.
Full text @ Luminescence